[an error occurred while processing this directive] EPON book - Table of Contents

Ethernet Passive Optical Networks

ISBN: 0071445625

Table of Contents


Part I:    Overview of Access Network Architectures

    1    Introduction
        1.1    Existing "Broadband" Solutions
            1.1.1    Digital Subscriber Line
            1.1.2    ADSL
            1.1.3    Community Antenna Television (CATV) networks
        1.2    Traffic Growth
        1.3    Evolution of the "First Mile"
            1.3.1    Fiber-to-the-Premises
            1.3.2    Next-Generation Subscriber Access Network
            1.3.3    PON is the Best Candidate
        References
    2    Overview of PON Enabling Technologies
        2.1    Optical Fiber
            2.1.1    Light Propagation in Fiber
            2.1.2    Single-Mode Fiber vs. Multi-Mode Fiber
            2.1.3    Modal Dispersion
            2.1.4    Chromatic Dispersion
        2.2    Optical Splitters/Combiners
        2.3    PON Topologies
        2.4    Spectrum Sharing vs. Time Sharing
            2.4.1    WDMA PON
            2.4.2    TDMA PON
        2.5    Burst-Mode Transceivers
        References
    3    Access Network Architectures based on TDMA PON
        3.1    ATM PON
        3.2    Ethernet PON
            3.2.1    Why Ethernet?
        3.3    GFP PON
        3.4    Comparison of BPON/GPON and EPON approaches
        References
    4    Emergence of Ethernet PON
        4.1    EPON Standardization
            4.1.1    Scope of Work
            4.1.2    Physical Medium Dependent (PMD) Sublayer
            4.1.3    Point-to-Multipoint Protocol
            4.1.4    Extensions of the Existing Clauses
                4.1.4.1    Reconciliation Sublayer (RS)
                4.1.4.2    Physical Coding Sublayer (PCS)
                4.1.4.3    Physical Medium Attachment (PMA) Sublayer
        4.2    EPON Today: Promise and Challenges
        References

Part II:    EPON Architecture

    5    EPON Overview
        5.1    Downstream Transmission
        5.2    Upstream Transmission
            5.2.1    Contention-Based vs. Guaranteed Media Access
            5.2.2    Centralized vs. Distributed Arbitration
        5.3    Multi-Point Control Protocol
            5.3.1    Bandwidth Assignment
                5.3.1.1    Pipelined Timeslot Assignment
                5.3.1.2    Decoupled Downstream and Upstream Timing
                5.3.1.3    MPCP Clock Synchronization
                5.3.1.4    Loop Timing
            5.3.2    Auto-Discovery
                5.3.2.1    Discovery Slot and Discovery Window
                5.3.2.2    Avoiding Persistent Collisions
            5.3.3    Round-Trip Time Measurement
                5.3.3.1    Timestamp Reference
    6    Logical Topology Emulation
        6.1    Point-to-Point Emulation (P2PE)
        6.2    Shared-Medium Emulation (SME)
        6.3    Combined P2PE and SME Mode
        6.4    Final Solution
            6.4.1    LLID Filtering Rules
        6.5    Preamble Format
            6.5.1    Start-of-LLID Delimiter
            6.5.2    Cyclic Redundancy Check
        References
    7    Laser Control Function
        7.1    Data Detector Function
        7.2    Data Detector State Diagram
            7.2.1    WAIT_FOR_CODE_GROUP State
                7.2.1.1    IsIdle(..) Function
            7.2.2    DATA_ARRIVAL State
            7.2.3    TURN_LASER_ON State
            7.2.4    IDLE_ARRIVAL State
            7.2.5    TURN_LASER_OFF State
            7.2.6    TRANSMIT_CODE_GROUP State
        7.3    FIFO Buffer Size
        References
    8    Multi-Point Control Protocol: A Formal Specification
        8.1    MPCP Frame Structure
            8.1.1    REPORT Control Frame
                8.1.1.1    Queue  n Report
                8.1.1.2    Report Bitmap
                8.1.1.3    Number of Queue Sets
            8.1.2    GATE Control Frame
                8.1.2.1    Number of Grants / Flags
                8.1.2.2    Grant  n Start Time
                8.1.2.3    Grant  n Length
                8.1.2.4    Sync Time
            8.1.3    REGISTER_REQ Control Frame
                8.1.3.1    Flags
                8.1.3.2    Pending Grants
            8.1.4    REGISTER Control Frame
                8.1.4.1    Assigned Port
                8.1.4.2    Flags
                8.1.4.3    Sync Time
                8.1.4.4    Echoed Pending Grants
            8.1.5    REGISTER_ACK Control Frame
                8.1.5.1    Flags
                8.1.5.2    Echoed Assigned Port
                8.1.5.3    Echoed Sync Time
        8.2    Opcode-Independent Processes
            8.2.1    Control Parser
                8.2.1.1    WAIT FOR RECEIVE State
                8.2.1.2    PASS TO MAC CLIENT State
                8.2.1.3    PARSE OPCODE State
                8.2.1.4    PARSE TIMESTAMP State
                8.2.1.5    Timestamp Drift Tolerance
                8.2.1.6    INITIATE MAC CONTROL FUNCTION State
            8.2.2    ONU Control Multiplexer
                8.2.2.1    INIT State
                8.2.2.2    TRANSMIT READY State
                8.2.2.3    PARSE OPCODE State
                8.2.2.4    MARK TIMESTAMP State
                8.2.2.5    CHECK SIZE State
                8.2.2.6    TRANSMIT FRAME State
                8.2.2.7    START PACKET INITIATE TIMER State
            8.2.3    Multi-Point Transmission Control
                8.2.3.1    INIT State
                8.2.3.2    WAIT PENDING State
                8.2.3.3    ENABLE State
                8.2.3.4    DISABLE State
            8.2.4    OLT Control Multiplexer
                8.2.4.1    INIT State
                8.2.4.2    WAIT FOR TRANSMIT State
                8.2.4.3    TRANSMIT READY State
                8.2.4.4    PARSE OPCODE State
                8.2.4.5    MARK TIMESTAMP State
                8.2.4.6    SEND FRAME State
                8.2.4.7    START PACKET INITIATE TIMER State
        8.3    Gating Process
            8.3.1    Gate Generation at the OLT
                8.3.1.1    WAIT State
                8.3.1.2    WAIT FOR GATE State
                8.3.1.3    SEND GATE State
                8.3.1.4    PERIODIC TRANSMISSION State
            8.3.2    Gate Reception at the ONU
                8.3.2.1    WAIT State
                8.3.2.2    WAIT FOR GATE State
                8.3.2.3    FLUSH State
                8.3.2.4    PARSE GATE State
                8.3.2.5    INCOMING GRANT state
            8.3.3    Grant Activation
                8.3.3.1    WAIT FOR GRANT State
                8.3.3.2    WAIT FOR START TIME State
                8.3.3.3    CHECK GATE TYPE State
                8.3.3.4    RANDOM DELAY State
                8.3.3.5    START TX State
                8.3.3.6    STOP TX State
                8.3.3.7    CHECK NEXT GRANT State
                8.3.3.8    HIDDEN GRANT State
                8.3.3.9    BACK TO BACK GRANT State
        8.4    Reporting Process
            8.4.1    Report Generation at an ONU
                8.4.1.1    WAIT State
                8.4.1.2    WAIT FOR REPORT State
                8.4.1.3    SEND REPORT State
                8.4.1.4    PERIODIC TRANSMISSION State
            8.4.2    Report Reception at the OLT
                8.4.2.1    WAIT State
                8.4.2.2    RECEIVE REPORT State
        8.5    Discovery Process
            8.5.1    Discovery Gate Generation at the OLT
                8.5.1.1    IDLE State
                8.5.1.2    SEND DISCOVERY GATE State
                8.5.1.3    DISCOVERY WINDOW State
            8.5.2    Request Reception at the OLT
                8.5.2.1    IDLE State
                8.5.2.2    ACCEPT REGISTER REQUEST State
                8.5.2.3    SIGNAL State
            8.5.3    Register Generation at the OLT
                8.5.3.1    WAIT FOR REGISTER State
                8.5.3.2    REGISTER State
            8.5.4    Final Registration at the OLT
                8.5.4.1    WAIT FOR GATE State
                8.5.4.2    WAIT FOR REGISTER_ACK State
                8.5.4.3    COMPLETE DISCOVERY State
                8.5.4.4    VERIFY ACK State
                8.5.4.5    DISCOVERY NACK State
                8.5.4.6    REGISTERED State
                8.5.4.7    DEREGISTER State
            8.5.5    Discovery Process at the ONU
                8.5.5.1    WAIT State
                8.5.5.2    REGISTERING State
                8.5.5.3    REGISTER_REQUEST State
                8.5.5.4    DENIED State
                8.5.5.5    RETRY State
                8.5.5.6    REGISTER_RENDING State
                8.5.5.7    REGISTER_ACK State
                8.5.5.8    NACK State
                8.5.5.9    REGISTERED State
                8.5.5.10    LOCAL DEREGISTER State
                8.5.5.11    REMOTE DEREGISTER State
                8.5.5.12    WATCHDOG TIMEOUT State
    9    Forward Error Correction
        9.1    Basics of FEC Coding
        9.2    Stream-based vs. Frame-based FEC
        9.3    FEC Frame Delineation
            9.3.1    Hamming Distance between FEC Delimiters
            9.3.2    Backward Compatibility
        9.4    Encoding Procedure
        9.5    Decoding Procedure
        References

Part III:    System-Level Issues

    10    EPON Encryption Mechanism
        10.1    Development of a Security Mechanism
        10.2    EPON-Specific Encryption
            10.2.1    Block Cipher Mode
                10.2.1.1    Cipher Input Values
                10.2.1.2    Cipher Counter Alignment
                10.2.1.3    Lifetime of a Key
            10.2.2    Downstream Encryption
            10.2.3    Upstream Encryption
            10.2.4    Key Exchange and Switch-Over Scheme
                10.2.4.1    Message Format
                10.2.4.2    Key Exchange Protocol Using ONU-Generated Key
                10.2.4.3    Key Exchange Protocol Using OLT-Generated Key
        10.3    Summary
        References
    11    Path Protection in EPON
        11.1    Unprotected Tree
        11.2    Protected Trunk
        11.3    Protected Branches
        11.4    Protected Trunk and Branches
        11.5    Protected Tree
        References

Part IV:    EPON Performance

    12    Baseline Efficiency
        12.1    Encapsulation Overhead
        12.2    Scheduling Overhead
            12.2.1    Control Channel Overhead
            12.2.2    Guard-Band Overhead
            12.2.3    Discovery Overhead
            12.2.4    Frame Delineation Overhead
        12.3    FEC Overhead
        12.4    Summary
        References
    13    Discovery Slot Allocation
        13.1    Pair-Wise Collision Probability
        13.2    Average Success Rate
        13.3    Efficiency of Discovery Slot size
        13.4    Optimal Discovery Slot Size
    14    EPON with Static Slot Assignment
        14.1    Introduction
        14.2    System Architecture
        14.3    Traffic Model
        14.4    Performance Analysis
            14.4.1    Average Packet Delay
            14.4.2    Average Queue Size
            14.4.3    Frame Loss
            14.4.4    Bandwidth Utilization
                14.4.4.1    Improving Utilization using Packet Scheduling
        14.5    Summary
        References
    15    EPON with Dynamic Slot Assignment
        15.1    DBA Algorithm
            15.1.1    Maximum Transmission Window
            15.1.2    Components of Packet Delay
            15.1.3    IPACT Allocation Disciplines
        15.2    Results from Simulation Experiments
            15.2.1    Performance of Limited Service
        15.3    Summary
        References
    16    Support for Differentiated Classes of Service
        16.1    Introduction
            16.1.1    Overview of IEEE 802.1D Support for COS
        16.2    System Architecture: Integrating Priority Queuing in EPON
            16.2.1    Traffic Modeling
        16.3    Packet Delay Analysis
            16.3.1    Light-Load Penalty
        16.4    Optimization Schemes
            16.4.1    Tandem Queuing
            16.4.2    CBR Credit
                16.4.2.1    Dynamics of Packet Preemption
            16.4.3    Bandwidth Utilization
        16.5    Summary
        References
    17    Objectives of EPON Scheduling Algorithm
        17.1    A Formal Definition of Fairness
        17.2    Fair Schedulers
            17.2.1    Direct (Single-Level) Schedulers
            17.2.2    Hierarchical (Multi-Level) Schedulers
                17.2.2.1    Sibling-Fair vs. Cousin-Fair Schedulers
        17.3    Summary
        References
    18    Cousin-Fair Hierarchical Scheduling in EPON
        18.1    Fair Queuing with Service Envelopes
            18.1.1    Phase 1 - Requesting Service
            18.1.2    Phase 2 - Granting Service
            18.1.3    Service Envelope Approximation Schemes
                18.1.3.1    Min-Error Approach
                18.1.3.2    Min-Points Approach
                18.1.3.3    Approximation Error
            18.1.4    FQSE Complexity
            18.1.5    Granting Schemes
        18.2    FQSE Adaptation for EPON
            18.2.1    Head-of-Line Blocking
            18.2.2    Bandwidth (Timeslot) Utilization
        18.3    FQSE Performance
            18.3.1    Fairness of FQSE
            18.3.2    Analysis of Cousin-Fairness
            18.3.3    Analysis of Fairness Bound
        18.4    Summary
        References
    19    Conclusion
        19.1    Upgrading EPON
        19.2    Open Access

    Appendix A: Characteristics of Network Traffic
        References
    Appendix B: Synthetic Traffic Generation
        References
    Bibliography

                                                                                                                                                               

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